The Industry Standard Architecture (ISA) specification is a conventional and widely-used configuration in a computer system for a system bus connecting a central processing unit (CPU) to various devices such as a disk controller circuit for one or more floppy disk drives. Under the ISA specification, the bus could carry out a direct memory access (DMA) read cycle, in which data was transferred from a local memory associated with the central processing unit across the system bus to the disk controller circuit for storage on a disk drive. In a DMA write cycle of the bus, data would be obtained from a disk drive, error-checked, and transferred across the system bus to the local memory. In a DMA verify cycle, substantially the same sequence as in a DMA write cycle would occur, except that the data would not be transferred across the system bus to the local memory. The purpose of the DMA verify cycle is to check data on the disk for errors.
Newer computer systems use an enhanced version of the ISA standard which is the Extended Industry Standard Architecture (EISA). The EISA standard is completely compatible with the ISA standard, and also includes some additional features. Under both standards, one or more devices commonly called "bus masters" can be coupled to the system bus and can take control of the system bus. However, certain features of the EISA standard have the effect of preventing the bus from responding as quickly as was possible under the ISA standard, which in particular means that data may not be transferred across the bus to or from the disk controller circuit as fast as was the case under the ISA standard. For example, under the ISA standard a disk controller was assured that the maximum time between successive transfers would not exceed 14.5 .mu.sec, whereas with the EISA standard the time between successive transfers can be as long as 30.9 .mu.sec, and in certain circumstances can be even longer. Consequently, a disk controller under the ISA standard could place a byte read from a disk in a register and expect that within 14.5 .mu.sec the byte would normally be picked up and that another byte read from disk could be placed in the register, whereas under EISA the first byte might not be picked up within 14.5 .mu.sec and could thus be irretrievably lost if it was replaced with the second byte after only 14.5 .mu.sec. In order to address this problem, a new integrated circuit was developed which contains an enhanced disk controller circuit.
The enhanced disk controller circuit includes a selectively actuable first-in/first-out (FIFO) memory, so that when data is being transferred across the bus from the disk controller, up to sixteen bytes read from the disk can be stored in the FIFO controller, thereby giving the DMA controller more time to pick up each byte. The enhanced disk controller circuit is capable of operating in an ISA compatible mode, and if the FIFO memory is disabled in this mode the disk controller circuit responds to DMA read, write and verify cycles in exactly the same manner as the disk controller circuit used in pre-existing computers with ISA buses. However, the enhanced disk controller is also capable of operating in additional modes, which were not present in pre-existing ISA machines and in which the FIFO memory can be enabled to facilitate successive transfers of multiple data bytes. Also, the FIFO could be enabled in the ISA compatible mode if the system is designed to allow it. Whenever the FIFO is enabled, the design of the enhanced controller circuit is such that it will operate properly if the system bus attempts to carry out an ISA-specific DMA read or write cycle, but will always automatically produce a forced error indication if the system bus attempts to carry out an ISA-specific DMA verify cycle.
This forced error indication is not a design flaw in the enhanced disk controller circuit, because if software programs are written to prevailing industry standards, they will not be attempting to carry out a DMA verify cycle when the FIFO of the enhanced disk controller circuit is enabled. However, there are some software publishers who distributed for ISA machines certain software programs which intentionally deviated from industry standards, and when these programs are used on EISA machines or on other machines using the enhanced disk controller circuit, they can cause the enhanced disk controller integrated circuit to produce false error conditions of the type just described. Although these false error conditions are due to poor software development techniques rather than to any design flaw in the enhanced disk controller integrated circuit, it is nevertheless desirable to suppress these false error indications so that even software programs which do not adhere to industry standards can be reliably run on machines using the enhanced disk controller circuit without generating false error indications.
A known approach to solving this problem is to provide a special error suppression circuit, which detects the occurrence of a DMA verify cycle, and which manipulates the signals supplied to the enhanced disk controller circuit so as to deceive the controller circuit into interpreting the cycle as a DMA write cycle. These known circuits have been adequate for their intended purposes, but have not been satisfactory in all respects. For example, one known circuit depends on the use of signals which are produced locally at the CPU but are not available on the system bus under the ISA or EISA standards, and thus this circuit cannot be used for a disk controller circuit which is to be added to the computer system in the form of a circuit board plugged into a connector slot on the system bus. Another known circuit uses only signals present on the system bus and thus can be used on a circuit card plugged into a connector slot, but may be itself deceived into interpreting a bus cycle produced under control of a bus master device as a DMA verify cycle, in which case it manipulates the signals to the disk controller circuit when it should not. Further, both approaches may in some circumstances cause three-state outputs of two different devices to try and drive a common bus simultaneously, which over time may damage the three-state devices. Moreover, both circuits may produce momentary spurious outputs to the disk controller circuit at points in time when they should not.
Accordingly, an object of the present invention is to provide an improved error suppression circuit which requires only signals present on an EISA bus, which can reliably distinguish a DMA verify cycle from bus master cycles, and which does not produce momentary spurious outputs.